Set up this design (USB Device for PL Data Acquisition on Zynq UltraScale+ MPSoC)

[farshideh kordi]

Hi, I need your help to set up USB3 for pl side, I set up all parts based on this page

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/968785932/USB+Device+for+PL+Data+Acquisition+on+Zynq+UltraScale+MPSoC

Now, I want to know when I apply these changes on usb_intr_example.c and build the code in vitis what do I need to do for test it ? Do I need to use petalinux for test this design?

[Mikael Sandberg]

Hi @farshideh kordi,

Welcome to Atlassian Community!

Your question is better suited for Xilinx Community Forums, my bet is that you ended up on the Atlassian Community because you clicked help and then Ask the community in Confluence.